1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a method of fabricating stacked capacitor in a memory device.
2. Description of Related Art
For a memory device such as dynamic random access memory (DRAM), generally, an array of capacitors on the substrate are storing the binary data by charging or discharging the capacitors. One capacitor acts one bit of memory for storing the binary data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d corresponding to the status of capacitor being xe2x80x9cchargedxe2x80x9d or xe2x80x9cdischargedxe2x80x9d, respectively. The action of read/write in the DRAM is done through a transfer field effect transistor (TFET), in which a source of the TFET is coupled to a bit line (BL), a drain is coupled to the capacitor and a gate is coupled to a word line (WL). The BL carries a voltage level to charge the capacitor through the TFET, where the TFET is selectively controlled by the WL to be activated or inactivated. Thus a writing action can be done. On the other hand, if one wants to read the binary data having been stored, the BL is switched to a comparator circuit, or a sense amplifier, to check the voltage status of the capacitor for the reading action. Therefore the charges stored in the capacitor is essential to a memory quality in the DRAM.
The charges stored in the capacitor depends on the capacitance of the capacitor. The capacitance is determined by the storing area of the storage electrode, the isolating reliability between an upper electrode and a lower electrode of the capacitor, and dielectric constant of dielectric, which has been chosen. To be able to store more data, the density of the capacitors used in the memory device tends to increase. This results in the storage charges would be decreased. If the storage charges can stay high, the affections of noise to the sense amplifier for reading can be effectively reduced and it is not necessary to refresh the voltage level of the capacitor, frequently.
While the integration is increasing, the size of memory cell in a DRAM is reduced, accordingly. As known by one skilled in the art, the reduced size of the capacitor gives a result of lower capacitance. If the capacitance is decreased, the soft error due to the a particles can happen with higher probability. Therefore, it is desired that a capacitor has a reduced size but can keep sufficient capacitance. In order to achieve this purpose, various capacitor structure designs have been proposed, such as a stacked capacitor. However, an efficient method to fabricate a desired capacitor structure is still under developing. A method to fabricate a stack capacitor has been disclosed in U.S. Pat. No. RE36786. However, the method is still not efficient to have the desired capacitance.
The invention provides a method for fabricating a capacitor in a memory device. The method includes providing a substrate, which has several conductive structures formed thereon. The conductive structure has a cap layer on top. A doped region is formed in the substrate between the conductive structures. A first dielectric layer is formed over the substrate and the conductive structures. The first dielectric layer is patterned to form an opening between the conductive structures, where the opening exposes the doped region of the substrate, the sidewalls of the conductive structures, and a portion of top surface of the conductive structures. A conductive plug fills the opening. A dielectric block formed on the conductive plug. A conductive spacer is formed on the sidewalls of the dielectric block. The conductive spacer has electrical contact to the conductive plug. The dielectric block is removed to further expose the conductive plug. A hemi-spherical grain (HSG) conductive layer is formed on the topographic surface of the substrate. A dielectric spacer is formed on sidewall of the conductive spacer to cover a portion of the HSG conductive layer. The dielectric spacer includes a material different to the first dielectric layer in significantly different etching ratio. An etching back process is performed to remove the HSG conductive layer without being covered by the dielectric spacer, so that the first dielectric layer and the conductive plug are exposed again. The dielectric spacer is removed using an etching process with an etching selectivity on the dielectric spacer. A second dielectric layer, serving as a capacitor dielectric, is formed over the substrate. A capacitor electrode layer is formed over the substrate.
In the foregoing, the conductive structure includes, for example, a gate electrode, a world line, or a conductive line. The first dielectric layer includes, for example, a two-layer structure with a lower dielectric layer surrounding the conductive structures, and an upper dielectric layer formed over the first dielectric layer and the conductive structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.